1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device having a test mode for screening the semiconductor memory device.
2. Description of the Related Art
The semiconductor memory device has recently been making further progress in increase of the capacity and the operation speed of semiconductor devices. Along with such progress, the configuration within the semiconductor device has been more refined and the voltage has been decreased. These semiconductor memory devices are provided to customers after defective products are screened out by subjecting produced semiconductor wafers to wafer testing and subjecting packaged devices to a screening test. However, defects may occur which are difficult to find by the wafer test or screening test.
One of such defects difficult to find is a bit-line to bit-line short defect of memory cells. Even if there is a short between bit lines, it will be very difficult to detect if the resistance value of the short is high. Additionally, a long test time is required to detect the short. When such defective semiconductor memory device is incorporated in electronic equipment, there is a risk that the resistance value at a part having the bit-line to bit-line short will be decreased to cause increase of leak current while the electronic equipment is used by the customer. Therefore, it is urgently desired to develop a technique capable of detecting a high resistance short in a screening test.
Patent Publication 1 (Japanese Laid-Open Patent Publication No. 2002-074995) for example relates to the bit-line to bit-line short defects. A defect detection method disclosed in this patent publication will be briefly described with reference to FIGS. 1 and 2. FIG. 1 is connection diagram showing components relating to memory bit lines in a semiconductor memory device, and FIG. 2 is a timing chart thereof. The memory arrays shown in FIG. 1 employ shared type sense amplifiers, whose connection with the bit lines is controlled by transfer gates TG.
The shared type sense amplifiers exchange data with memory cells by switching and connecting bit lines of a selected memory array by means of the transfer gates TG. When a central memory array is selected, the transfer gates TGL and TGR are activated and connected to the sense amplifiers SA. If a left or right memory array is selected, a transfer gate TGL0 or TGR0 is activated and connected to the sense amplifier SA.
FIG. 2A shows a timing chart of a first embodiment of the prior art, while FIG. 2B shows a timing chart of a second embodiment of the prior art. FIGS. 2A and 2B illustrate signal waveforms of (a) a command, (b) a bank control signal, (c) a memory array selection signal, (d) a word line, (e) the transfer gates (f) the sense amplifier, (g) the first bit line, and (h) the second bit line. The description here will be made of a case where bit-line to bit-line short has occurred between the first and second bit lines (BL1 and BL2).
Referring to FIG. 2A, the detection of high resistance short is carried out as follows: The transfer gates TGR and TGL are turned OFF by the falling edge of a write (or read) command with the word line kept in the selected state. This state is kept for a predetermined time and then changed to the pre-charge state after the word line is placed in the non-selected state.
A description will be made of a principle why the operation described above enables the detection of high resistance short between the bit lines. The turning OFF of the transfer gates TGR and TGL cuts the connection of the sense amplifier from the bit lines, whereby the bit lines are rendered floating. In this state, the adjacent bit lines are made to have data of opposite logic values (by writing or reading).
When there is a relatively high-resistance short between the bit lines, for example, electric current flows from the memory cell bit line in which data of logic value “1” is written to the memory cell bit line in which data of logic value “0” is written. As shown by J1 and J2 in FIG. 2A, the voltages of these bit lines are canceled with each other. This causes the bit lines BL1 and BL2 to become an intermediate level that cannot be determined either as a high level or as a low level. When voltages of these bit lines at the intermediate level are stored in a memory cell, data corruption will occur in the memory cell. Accordingly, the data corruption due to the bit-line to bit-line short can be found when the data is read subsequently.
In the prior art second embodiment shown in FIG. 2B, when the word line is activated, minute potential differences J3 and J4 are generated in the bit line pairs due to the charge in the memory cells. Normally, the sense amplifiers SA should be activated at the time when the minute potential differences J3 and J4 are generated in the bit line pairs. However, in the test mode according to the prior art, the sense amplifiers SA are not activated. Therefore, the minute potential differences J3 and J4 disappear by being cancelled by the bit-line to bit-line short, and the potential of the bit lines becomes an intermediate potential. The sense amplifiers SA are activated after a delay of time T2 from the rising of the word line. Since the bit lines are at the intermediate potential, the memory cell data cannot be read correctly. This makes it possible to find the data corruption due to the bit-line to bit-line short.
Although the bit-line to bit-line short can be detected, as described above, the implementation of the prior art involves two major problems. One of the problems relates to the fact that, in short detection, the transfer gates TG or the sense amplifiers SA are turned off to render the bit lines floating, and the charges in the bit lines are charged or discharged, and canceled with each other by resistance shorting between the bit lines which are in the floating state. The charge/discharge time is determined based on a time constant τ that is determined by the value of the shorting resistance and the capacity of the bit lines. The resistance value is originally high, and hence the time constant τ becomes a large time constant. This means that it takes a long time to detect the bit-line to bit-line short. Moreover, the resistance value, including variations thereof, must be estimated preliminarily in the course of designing.
Another problem relates to the fact that it is uncertain whether the intermediate level of the memory cell is determined to be either high level or low level by the sense amplifier SA. The sense amplifier SA always determines unambiguously whether the level is high or low. In the case of the intermediate level, however, it is ambiguous whether the bit lines are determined to be either high level or low level depending on the offset of the sense amplifier SA and surrounding noises. This makes it difficult to obtain reliable defect detection results. In this manner, the difficulty to produce a difference in potential between adjacent bit lines induces a problem that the detection sensitivity is low. Thus, according to the prior art, it takes a long time to obtain a detection result, and the detection sensitivity is low due to the difficulty to produce a difference in potential between adjacent bit lines. In conclusion, the prior art is not free of the problem the difficulty in detection of the bit-line to bit-line short.
As described above, the conventional semiconductor memory devices have problems that the bit-line to bit-line short in a memory cell is difficult to detect due to its large resistance value, and a long test time is required.